Memory devices generally comprise an array of memory cells, each memory cell storing one bit of data. SRAM (Static Random Access Memory) is an example of a type of volatile memory array that provides a relatively compact means of storing data.
There are a number of drawbacks of memory arrays such as SRAM arrays. In particular, read operations tend to be relatively slow due to the use of common bit lines for writing to the memory cells and reading data stored by the memory cells, which must be charged and discharged. Furthermore, it is not possible to read more that one memory cell in a given column of the memory array at once. A further drawback is that in order to perform a global reset of the memory device, it is necessary to address each word line of the memory cell in turn and write the reset value (for example a logic 0), which is a time consuming process.
Similarly, testing of such memory arrays is relatively slow and complex, as this involves performing a write and read operation to each memory cell in turn.
There is thus a need in the art for an improved memory array overcoming one or more of these drawbacks.